Semiconductor chips have become progressively more complex, driven in large part by the need for increasing processing power in a smaller chip size for compact or portable electronic devices such as cell phones, smart phones, personal media systems, ultraportable computers.
Stacking multiple chips in a single package can help meet the need for smaller package sizes. One method for increasing chip density is a package-on-package-mold embedded package (PoP-MeP) where a chip is embedded in molding compound and an interposer is placed on the molding compound and connected to a substrate under the molding compound. Another package is then connected to the interposer. However, the necessity of routability of inputs and outputs through the interposer can lead to greater cost of a laminate interposer or substrates.
Thus, a need still remains for a simpler and cheaper method of manufacturing interposer substrates. In view of the increasing demands placed on semiconductor chips, it is increasingly critical that answers be found to these problems. In view of the ever-increasing commercial competitive pressures, along with growing consumer expectations and the diminishing opportunities for meaningful product differentiation in the marketplace, it is critical that answers be found for these problems. Additionally, the need to reduce costs, improve efficiencies and performance, and meet competitive pressures adds an even greater urgency to the critical necessity for finding answers to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.